1. Field of the Invention
The present invention relates generally to the field of integrated circuit (IC) design. In particular, the present invention relates to differential signal line design for multi giga-hertz GHz data rates on the high performance IC packages.
2. Related Art
For high pin-count packages, a significant challenge lies in escaping high data rate input/output (IO) differential signals from the IC, or die, to the package. In escaping these high data rate signals, a designer will preferably provide for escaping the signals without impacting signal integrity.
Using conventional techniques, signals are escaped from the die near the die-package interface with virtually no concern for signal integrity. This approach might be suitable for relatively low frequency signals, i.e., signals having data rates below one giga-bit per second (Gbps). But as the signal data rates increase, for example, beyond about 5 Gbps, the methodology for escaping the signals from the die becomes absolutely critical.
Because of limited space on the die, the signals are traditionally routed without concern for line factors such as characteristic impedance and the cross-talk between adjacent signal lines. Unfortunately, however, these factors degrade signal quality by producing unwanted reflections due to the impedance mismatches, and signal coupling between the adjacent lines.
What is needed, therefore, is a technique for escaping high data rate differential signals while, at the same time, maintaining signal integrity. More specifically, what is needed is a technique for providing substantially uniform impedances across all portions of the signal lines used to escape high data rate differential signals. Finally, what is needed is a technique that minimizes cross-talk between adjacent signal lines carrying the differential signals.